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117 lines
2.5 KiB
ArmAsm
117 lines
2.5 KiB
ArmAsm
#include "arm_arch.h"
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.text
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.fpu neon
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.code 32
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.global gcm_init_v8
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.type gcm_init_v8,%function
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.align 4
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gcm_init_v8:
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vld1.64 {q9},[r1] @ load H
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vmov.i8 q8,#0xe1
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vext.8 q3,q9,q9,#8
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vshl.i64 q8,q8,#57
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vshr.u64 q10,q8,#63
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vext.8 q8,q10,q8,#8 @ t0=0xc2....01
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vdup.32 q9,d18[1]
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vshr.u64 q11,q3,#63
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vshr.s32 q9,q9,#31 @ broadcast carry bit
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vand q11,q11,q8
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vshl.i64 q3,q3,#1
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vext.8 q11,q11,q11,#8
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vand q8,q8,q9
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vorr q3,q3,q11 @ H<<<=1
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veor q3,q3,q8 @ twisted H
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vst1.64 {q3},[r0]
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bx lr
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.size gcm_init_v8,.-gcm_init_v8
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.global gcm_gmult_v8
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.type gcm_gmult_v8,%function
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.align 4
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gcm_gmult_v8:
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vld1.64 {q9},[r0] @ load Xi
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vmov.i8 q11,#0xe1
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vld1.64 {q12},[r1] @ load twisted H
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vshl.u64 q11,q11,#57
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#ifndef __ARMEB__
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vrev64.8 q9,q9
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#endif
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vext.8 q13,q12,q12,#8
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mov r3,#0
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vext.8 q3,q9,q9,#8
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mov r12,#0
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veor q13,q13,q12 @ Karatsuba pre-processing
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mov r2,r0
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b .Lgmult_v8
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.size gcm_gmult_v8,.-gcm_gmult_v8
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.global gcm_ghash_v8
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.type gcm_ghash_v8,%function
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.align 4
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gcm_ghash_v8:
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vld1.64 {q0},[r0] @ load [rotated] Xi
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subs r3,r3,#16
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vmov.i8 q11,#0xe1
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mov r12,#16
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vld1.64 {q12},[r1] @ load twisted H
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moveq r12,#0
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vext.8 q0,q0,q0,#8
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vshl.u64 q11,q11,#57
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vld1.64 {q9},[r2],r12 @ load [rotated] inp
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vext.8 q13,q12,q12,#8
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#ifndef __ARMEB__
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vrev64.8 q0,q0
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vrev64.8 q9,q9
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#endif
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veor q13,q13,q12 @ Karatsuba pre-processing
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vext.8 q3,q9,q9,#8
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b .Loop_v8
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.align 4
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.Loop_v8:
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vext.8 q10,q0,q0,#8
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veor q3,q3,q0 @ inp^=Xi
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veor q9,q9,q10 @ q9 is rotated inp^Xi
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.Lgmult_v8:
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.byte 0x86,0x0e,0xa8,0xf2 @ pmull q0,q12,q3 @ H.lo·Xi.lo
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veor q9,q9,q3 @ Karatsuba pre-processing
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.byte 0x87,0x4e,0xa9,0xf2 @ pmull2 q2,q12,q3 @ H.hi·Xi.hi
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subs r3,r3,#16
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.byte 0xa2,0x2e,0xaa,0xf2 @ pmull q1,q13,q9 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
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moveq r12,#0
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vext.8 q9,q0,q2,#8 @ Karatsuba post-processing
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veor q10,q0,q2
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veor q1,q1,q9
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vld1.64 {q9},[r2],r12 @ load [rotated] inp
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veor q1,q1,q10
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.byte 0x26,0x4e,0xe0,0xf2 @ pmull q10,q0,q11 @ 1st phase
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vmov d4,d3 @ Xh|Xm - 256-bit result
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vmov d3,d0 @ Xm is rotated Xl
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#ifndef __ARMEB__
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vrev64.8 q9,q9
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#endif
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veor q0,q1,q10
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vext.8 q3,q9,q9,#8
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vext.8 q10,q0,q0,#8 @ 2nd phase
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.byte 0x26,0x0e,0xa0,0xf2 @ pmull q0,q0,q11
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veor q10,q10,q2
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veor q0,q0,q10
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bhs .Loop_v8
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#ifndef __ARMEB__
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vrev64.8 q0,q0
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#endif
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vext.8 q0,q0,q0,#8
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vst1.64 {q0},[r0] @ write out Xi
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bx lr
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.size gcm_ghash_v8,.-gcm_ghash_v8
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.asciz "GHASH for ARMv8, CRYPTOGAMS by <appro@openssl.org>"
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.align 2
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